The invention pertains to a circuit configuration for selectively transmitting information items from a measuring device to chips on a wafer, to a wafer having a plurality of chips for use with such a circuit configuration, and to a system having such a circuit configuration and such a wafer.
It has been known heretofore that a plurality of identical chips which have been fabricated as memory components, for example, are contact-connected simultaneously by a corresponding measuring device and measured with the predetermined identical parameters. This method can reduce the relatively high testing costs in particular for functional tests on the wafer, since the test capacity and thus the throughput can be considerably increased by virtue of the parallel testing. However, if a partly defective chip is identified during the testing procedure, then there is the problem of identifying in a targeted manner the defective component from the plurality of chips which are tested in parallel.
In the case of memory components having a high storage capacity, in particular, a few individual memory cells, for example, may be defective. The defective cells can be disabled or repaired by repair files that are to be input. The chip does not incur any quality losses as a result of this since the repaired cells can no longer be identified afterward. Moreover, in the case of DRAM memories (Dynamic Random Access Memories) it can happen that one chip requires a different voltage trimming in order to achieve its full functionality. These problems can likewise be eliminated by corresponding trimming files if there is access to the individual chip via data and command lines.
In state of the art test systems, although the required files can be transmitted to an individual chip, this nonetheless requires a separate control unit in addition to the measuring device, which control unit manages the individual driver channels for all the contact-connected chips and controls them correspondingly according to a defect that is present. Moreover, this additional control unit can be utilized exclusively for individual data transmission. A control unit of this type is relatively complicated and leads to undesired costs as a result of the additional programs that are required.
U.S. Pat. No. 6,064,213 discloses a circuit configuration for selectively transmitting information items from a measuring device to chips on a wafer, generically referred to as a wafer-level burn-in test device. There, a plurality of chips can be simultaneously contact-connected via assigned contact arrays of a needle card and can be measured in parallel by the measuring device. A plurality of memories are each assigned to a contact array on the needle card. The measuring device is configured to transmit information items for a selected chip individually via the assigned memory to the chip. That is, in the configuration, each contact array of a needle card is assigned an external module with a storage functionality, a measuring device being designed for transmitting information items to a selected chip on a wafer individually via the assigned external module. German published patent application DE 42 13 905 A1 discloses using a shift register for converting a serial data stream in an external module with storage functionality.
It is accordingly an object of the invention to provide a simple and cost-effective circuit configuration for selectively transmitting information items from a measuring device to chips on a wafer, which overcomes the above-mentioned disadvantages of the heretofore-known devices and methods of this general type and wherein the measuring device enables a plurality of chips to be tested simultaneously. It is a further object to provide a wafer having a plurality of chips for use with such a circuit configuration, and a system having such a circuit configuration and such a wafer.
With the foregoing and other objects in view there is provided, in accordance with the invention, a circuit configuration for selectively transmitting information items from a measuring device to chips on a wafer, comprising:
a needle card having a plurality of contact arrays configured to simultaneously contact a plurality of chips on the wafer;
a measuring device connected to the needle card and configured to measure the plurality of chips on the wafer in parallel via the contact arrays;
a plurality of memories each assigned to a respective the contact array on the needle card, the measuring device being connected to transmit information items for a selected chip individually via a respective the assigned memory to the chip; and
each of the memories having an input and an output, and the plurality of memories being connected up sequentially, with the output of a respective the memory connected to the input of a succeeding the memory.
There is also provided, in accordance with the invention, a wafer for use with the above circuit configuration. The wafer has a plurality of chips (i.e., integrated circuits) each having an internal memory.
With the above and other objects in view there is also provided, in accordance with the invention, a wafer-level testing system, comprising a circuit configuration and a wafer as outlined above. That is:
a wafer with a plurality of chips each having an internal memory;
a needle card having a plurality of contact arrays configured to simultaneously contact a plurality of the chips on the wafer;
a measuring device connected to the needle card and configured to measure the chips on the wafer in parallel via the contact arrays;
a plurality of memories each assigned to a respective the contact array on the needle card, and each of the memories having an input and an output, and the plurality of memories being connected up sequentially, with the output of a respective the memory connected to the input of an adjacent the memory, and with the output of a respective the memory connected to an input of a respective the internal memory of the succeeding chip.
In other words, in the case of the novel configuration of the memory arrangement, a plurality of memories are connected up sequentially, so that the output of a memory is connected to the input of a succeeding memory. As a result, the information present at the output is transmitted onto the succeeding memory with the next clock signal.
In the case of the novel configuration of the wafer, each chip has an internal memory to which the information items can be transmitted in parallel from the memories of the circuit configuration. In the case of memory chips, this function can advantageously be performed by the memory cells present.
The novel circuit configuration for selectively transmitting information items to one of a plurality of chips of a wafer which are measured in parallel, the novel wafer for use with such a circuit configuration, and the novel system having such a circuit configuration and such a wafer have the advantage that an additional control unit can be dispensed with. Each chip which is contact-connected in parallel can nevertheless be addressed individually by the measuring device and any desired information items such as files and commands can be transmitted to the selected chip. As a result, not only are costs for an additional controller obviated, but also the programming is considerably simplified in an advantageous manner.
It is further regarded as particularly advantageous that the external memories are configured as shift registers. Shift registers are simple circuits wherein an information item applied to the input can be advanced with each clock cycle. The number of clock cycles thus determines, in a simple manner, the chip to which the information items are to be transmitted. In this way, it is advantageously possible to select an individual chip for the transmission of information items.
It is also favorable for the internal memories of the chips to be designed as shift registers. The information intended for an individual chip is stored thereby.
Since the outputs of the internal memories of the chips are open and the output of an external memory is connected to the input of the succeeding chip and thus the input of the succeeding internal memory, the information present always passes in a simple manner directly to an individual chip. An individual chip can be individually addressed in this way.
Since the measuring device knows the present data of the chips which are tested in parallel, it can also advantageously generate the information items which are to be transmitted to an individual chip.
In order that the information items, which are sent as a data string from the measuring device, can be transmitted to the desired chip, the input of the first external memory and the input of the first chip or the internal memory thereof are connected in parallel and connected to the measuring device.
By virtue of the sequential transmission of the information items to all the external memories, each chip advantageously receives the individual information intended for it.
The sequential transmission of the information items to all the external and internal memories furthermore has the effect that the information items input first pass to the internal memory of the last contact-connected chip.
On the other hand, it is also advantageous that the information items input last are transmitted to the internal memory of the first chip. As a result, the information items can be controlled in a targeted manner.
A further advantage also exists if the circuit configuration is employed for chips which are designed as memory modules such as DRAMs. These modules are clocked dynamically and can easily store the information items received. An additional memory is then no longer necessary.
A particularly favorable solution is produced if the information items contain data which can be used, for example, to repair an individual chip. In that case, the chip is not lost, so that the yield can easily be increased by means of the repair method.
It is also favorable to carry out the transmission of information items to an individual chip which contain data for voltage trimming. Since certain process tolerances always have to be expected on account of the fabrication process, a simple correction of the voltage can advantageously be carried out even after the completion of the chips.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a circuit configuration for selectively transmitting information items from a measuring device to chips on a wafer during chip fabrication, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.